1. Field of the Invention
The present invention relates to a logic circuit which includes at least one synchronous flip-flop.
2. Description of the Related Art
A four-bit shift register is known as one example of a CMOS (Complementary Metal-Oxide Semiconductor) logic circuit including synchronous flip-flops which are synchronized with clock signals. This four-bit shift register is arranged to have four synchronous D-type flip-flops F1, F2, F3 and F4. The flip-flops F1, F2, F3 and F4 are sequentially connected to each other. That is, the flip-flop F1 is serially connected to the flip-flop F2. The flip-flop F2 is connected serially to the flip-flop F3. The flip-flop F3 is serially connected to the flip-flop F4. Each of the four synchronous D-type flip-flops is connected to an inverter. The inverters supply a clock signal to each flip-flop. In an initial state that each of the flip-flops outputs a low-level signal, when a data signal which is input to the flip-flop F1 rises to a high level, at first, the flip-flop F1 latches the high-level data signal at the leading edge of the clock signal and outputs a high-level output signal H1. The flip-flop F2 latches the high-level signal H1 sent by the flip-flop F1 at the next leading edge of the clock signal and outputs a high-level output signal H2. Likewise, the remaining flip-flops F3 and F4 serve to output their high-level output signals H3 and H4 in the same process as above.
Conversely, when the data signal lowers to a low level, those flip-flops F1 to F4 serve to sequentially output the low-level signals L1 to L4 as being synchronized with the clock signals. That is to say, the data signal input to the flip-flop F1 is shifted to the next flip-flops as being synchronized with each leading edge of the clock signals so that the flip-flops F1 to F4 serve to output parallel signals in sequence.
The aforementioned shift register is arranged to inevitably receive a clock signal even when the data signal input to each flip-flop has the same logic level as the output signal of each flip-flop, therefore, in the case that no flip-flops are required to change their states. The clock signals input to the flip-flops result in charge and discharge currents flowing in internal circuits of the flip-flops, which thereby consumes power. As such, the logic circuit is arranged so that a clock signal is input to the flip-flops of the logic circuit if not necessary, which results in the idle current flowing in the logic circuit.
The shift register needs an inverter arranged to have a CMOS transistor of a large driving capacity, for supplying clock signals to the flip-flops F1 to F4 of the shift register. Such a CMOS transistor having a large driving capacity entails flow of a large through current in internal circuits of the flip-flops when the clock signal is reversed. It is another disadvantageous factor of increasing the idle current, that is, of increasing the power consumption.